Fabricating semiconductor devices such as logic and memory devices typically includes processing a specimen such as a semiconductor wafer using a number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that typically involves transferring a pattern to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a semiconductor wafer and then separated into individual semiconductor devices.
During each semiconductor fabrication process, defects such as particulate contamination and pattern defects may be introduced into semiconductor devices. Such defects may be found either randomly on a specimen surface or may be repeated within each device formed on a specimen. For example, random defects may be caused by events such as an unexpected increase in particulate contamination in a manufacturing environment and an unexpected increase in contamination in process chemicals that may be used in fabrication of a semiconductor device. A number of tools have been developed to inspect wafers for such defects.
In addition, as integrated circuit device geometries continue to shrink, it has become more important to perform metrology following each fabrication step, e.g., to verify that design features are properly printed or that features in successive layers are properly aligned with respect to each other. Manufacturers often use optical techniques to perform non-destructive inspection and analysis of semiconductor wafers. Such techniques often require a feature to be purpose-built on the wafer for use as a standard for calibration of tools performing inspection or metrology.
Prior inspection and metrology methods place targets for metrology or proxies for inspection in the scribe lines between adjacent die or at predetermined test sites in the die. Targets or proxies placed in scribe lines may be less accurate in predicting actual chip performance and yield than targets in the die. Methods have been proposed to automatically generate recipes for CD-SEM metrology where a set of specific metrology locations are input into the recipe in advance. However, placing metrology targets or inspection proxies in the die is a technically difficult procedure due to process compatibility and space restrictions.
It is within this context that embodiments of the present invention arise.